1. Field of the Invention
The invention generally relates to integrated circuit structures, and more particularly, to an integrated circuit structure comprising multiple non-planar semiconductor bodies with different thicknesses and with variable spacing between the semiconductor bodies.
2. Description of the Related Art
Integrated circuit design decisions are often driven by device scalability and manufacturing efficiency. For example, multi-gated non-planar field effect transistors (FETs), such as double gate or tri-gate FETs, were developed to provide scaled devices with larger drive currents and reduced short channel effects over planar FETs. Double gate FETs (e.g., fin-type FETs (finFETs) are non-planar transistors in which a channel is formed in a center region of a thin semiconductor fin with source and drain regions at opposing ends. Gates are formed on the opposing sides of the thin semiconductor body adjacent the channel. The effective fin width is determined by height (e.g., short wide fins can cause partial depletion of a channel). For a double-gated fin-FET the fin thickness is generally one-fourth the length of the gate or less to ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. Additionally, the effective channel width of a finFET device can be increased by using multiple fins.
Trigate MOSFETs have a similar structure to that of finFETs; however, the semiconductor fin width and height are approximately the same (e.g., the fin width can be approximately ½ to two times the height) so that gates can be formed on three sides of the channel, including the top surface and the opposing sidewalls. As long as the height of the channel is generally not less than the width, the channel will remain fully depleted and the three-dimensional field effects of a trigate MOSFET will give greater drive current and improved short-channel characteristics over a planar transistor. As with finFETs, the effective channel width of a trigate MOSFET can be increased by using multiple fins.
Current technology allows an integrated circuit structure to be designed and formed with multiple non-planar devices (e.g., finFETs or trigate FETs) on the same silicon-on-insulator (SOI) wafer but generally limits such structures to devices having the same fin width and to devices having approximately uniform spacing between the fins. However, there are a variety of applications that could benefit from an integrated circuit structure that has multiple fins with different thicknesses and that further has variable spacing between the fins. For example, different fin widths could be used to control depletion of different FETs in an integrated circuit or could be used in diffusion resistors. Additionally, variable fin to fin spacing could be incorporated into a fin to fin capacitor or into a precision resistor. Therefore, there is a need for a integrated circuit structure that has multiple semiconductor fins on the same substrate with different fin thicknesses and with variable spacing between the fins.